Transparent Clock

IEEE-1588v2-2008 defines a Transparent Clock (TC) as a device that measures the time taken for a PTP event message to transit the device, and provides this information to clocks receiving this PTP event message.

Refer to the RUCKUS FastIron Features and Standards Support Matrix for more information about the supported devices.

The following figure shows a typical clock distribution topology in the network.

Typical Clock Distribution Topology

  1. GM- Grandmaster clock-regional
  2. BC- Boundary Clock
  3. TC- Transparent Clock
  4. S- Slave Clock
  5. Y - End Device

The following figure shows a clock topology with redundant clock sources in the network.

Topology with Redundant Clock Sources

  1. GM- Grandmaster Clock
  2. BC- Boundary Clock
  3. TC- Transparent Clock
  4. S- Slave Clock

End-To-End Delay Mechanism

The following figure shows an ideal End-to-End delay mechanism.

End-to-End Delay Mechanism

  1. The master clock sends a SYNC message to the slave device. As the SYNC message leaves the physical interface of the master clock, it captures a timestamp (t1).
  2. The slave clock receives the SYNC message and the clock captures the time (t2) when the SYNC message arrives at its physical port. Due to the propagation delay in the wire, there will be a slight time difference between the slave timestamp clock and the master clock.
  3. A delay request message is then sent to the master clock to the slave clock to calculate the time difference between them. The slave clock running timestamp captures the time (t3) as soon as the message starts transmitting out the physical interface of the slave.
  4. The master clock receives the delay request and uses the master clock running timestamp to capture the time (t4) when the message starts receiving on its physical interface.
  5. The master clock sends the slave clock a delay response message containing the captured t4 value. The slave clock receives the delay response message with the t4 value and adjusts itself to synchronize with the master clock.

IEEE-1588v2 Message Format

The following figure shows the common message format according to IEEE-1588v2-2008.

Message Format

Bits Octets Offset
7 6 5 4 3 2 1 0
transportSpecific messageType 1 0
reserved versionPTP 1 1
messageLength 2 2
domainNumber 1 4
reserved 1 5
flagField 2 6
correctionField 8 8
reserved 4 16
sourcePortIdentity 10 20
sequenceId 2 30
controlField 1 32
logMessageInterval 1 33

The End-to-End Transparent Clock Overcomes Clock Errors

When the PTP event message flows continuously through a network, it experiences packet delay and latency. The PTP-TC-enabled devices can overcome this delay by adjusting the correctionField in the PTP message to compensate for the residence time within the network. The PTP-TC is implemented as part of the Packet Processor. The ICX software enables the timestamping capability on a given port based on the user input or configuration. The implementation of the end-to-end transparent clock requires the residennce time of the device, which is the time it takes the event message from ingress port to egress port, and adding the calculated residence time to the correctionField of the event message. The end-to-end transparent clock uses the SYNC, DELAY_REQ, and DELAY_RESP event messages.

Residence time: A transparent clock generates an ingress timestamp when a PTP event message reaches the ingress port, and generates an egress timestamp when the PTP event message leaves the egress port. The residence time for each PTP event message can be computed for each egress port. The residence time is equal to the egress timestamp minus the ingress timestamp.

Note: The egress timestamp has a different value on each egress port of the transparent clock.

One-step transparent clocks: The residence time can be added to the correctionField of the Sync event message by the egress port during the transmission of the Sync message. The egress port can make any required corrections to the fields in the Sync message.

Note: The data type of the correctionField allows the residence time to be expressed to a fraction of a nanosecond, if this accuracy is supported by the transparent clock.

End-to-End Transparent Clock Recovery Mechanism

  1. TP- Timestamp Point
  2. MII - MAC Interface

The following topology shows the use case of PTP-TC using the ICX devices supporting PTP.

Network Topology with Transparent Clock Using ICX 7850 Units

PTP packet prioritization and end-to-end transparent clock is supported by the following RUCKUS devices in both standalone and stacking topology.

FastIron releases and supported platforms

Supported platforms FastIron release
FastIron 08.0.95 FastIron 08.0.95c

ICX7150-24 (non-PoE)

 Yes Yes

ICX7150-24P

 No Yes

ICX7150-48PF

 No Yes

ICX7150-C12P

 Yes Yes

ICX7150-C10ZP

 No Yes
ICX7850-32Q Yes Yes

ICX7850-48F

 Yes Yes
ICX7850-48FS No Yes

FastIron 08.0.95 allows updates to the correctionField on PTP event messages for the following types of PTP packets:

  • Ethernet frame with EtherType of 0x88F7.
  • Support PTP messages with MAC addresses as specified in the following table.

    Message Type and MAC Address

    Message Type MAC Address
    All except peer delay 01-1B-19-00-00-00
    Peer delay messages 01-80-C2-00-00-0E

FastIron 08.0.95 supports timestamping of PTP messages on ingress and egress ports, provided the PTP-TC is enabled on the participating ports.

Note: The supported RUCKUS ICX devices do not participate in generation or consumption of any PTP messages. The packets are generated between master and slave or client clock devices.

FastIron 08.0.95 supports the end-to-end PTP-TC mode of operation for standalone and stacking topologies. The software treats the stacking as a chain of PTP-TC devices connected back to back, and each device updates the correctionField to eliminate the residence time within the switch.

FastIron 08.0.95 automatically assigns the highest priority to the PTP messages that are untagged, or if they are not part of the IEEE 802.1Q encapsulated frame. The messages encapsulated as part of the IEEE 802.1Q frame follow the IEEE 802.1p priority carried in the Ethernet frame.

Parent topic: Precision Time Protocol