debug mstp msti

Displays information for a specific MSTP instance.
Syntax
debug mstp msti decimal
no debug mstp msti decimal
Parameters
decimal
Specifies the following values:
Value 0 for the Common and Internal Spanning Tree (CIST)
Value from 1 through 4094 for the Multiple Spanning Tree Instance (MSTI).
Modes

Privileged EXEC mode

Examples
device#debug mstp msti 0
MSTP debugging turned on for instances 0

If this command is enabled, output similar to the following is displayed. 

device#debug mstp msti 2
MSTP debugging turned on for instances 2 ,0
device# debug mstp enable
device# debug mstp events
MSTP Event debugging ON
device# MSTP[0x175f15]: PTX IDLE->TRANSMIT_PERIODIC - Port 1/1/1
MSTP[0x175f15]: PTX IDLE->TRANSMIT_PERIODIC - Port 1/1/2
MSTP[0x175f21]: PRX RECEIVE->RECEIVE - Port 1/1/1
MSTP[0x175f21]: PIM CURRENT->RECEIVE - MST 0, Port 1/1/1
MSTP[0x175f21]: PIM RECEIVE->REPEATED_DESIGNATED - MST 0, Port 1/1/1
MSTP: mstp_updtRcvdInfoWhileCist mst=0, Port 1/1/1, rcvdInfoWhile 5->7
MSTP[0x175f21]: PIM CURRENT->RECEIVE - MST 2, Port 1/1/1
MSTP[0x175f21]: PIM RECEIVE->REPEATED_DESIGNATED - MST 2, Port 1/1/1
MSTP: mstp_updtRcvdInfoWhileMsti mst=2, Port 1/1/1, rcvdInfoWhile 4->7
MSTP[0x175f21]: PRX RECEIVE->RECEIVE - Port 1/1/2
MSTP[0x175f21]: PIM CURRENT->RECEIVE - MST 0, Port 1/1/2
MSTP[0x175f21]: PIM RECEIVE->REPEATED_DESIGNATED - MST 0, Port 1/1/2
MSTP: mstp_updtRcvdInfoWhileCist mst=0, Port 1/1/2, rcvdInfoWhile 5->7
MSTP[0x175f21]: PIM CURRENT->RECEIVE - MST 2, Port 1/1/2
MSTP[0x175f21]: PIM RECEIVE->REPEATED_DESIGNATED - MST 2, Port 1/1/2
MSTP: mstp_updtRcvdInfoWhileMsti mst=2, Port 1/1/2, rcvdInfoWhile 4->7
MSTP[0x175f29]: PTX IDLE->TRANSMIT_PERIODIC - Port 1/1/1
MSTP[0x175f29]: PTX IDLE->TRANSMIT_PERIODIC - Port 1/1/2
noMSTP[0x175f35]: PRX RECEIVE->RECEIVE - Port 1/1/1
MSTP[0x175f35]: PIM CURRENT->RECEIVE - MST 0, Port 1/1/1
MSTP[0x175f35]: PIM RECEIVE->REPEATED_DESIGNATED - MST 0, Port 1/1/1
MSTP: mstp_updtRcvdInfoWhileCist mst=0, Port 1/1/1, rcvdInfoWhile 5->7
MSTP[0x175f35]: PIM CURRENT->RECEIVE - MST 2, Port 1/1/1
MSTP[0x175f35]: PIM RECEIVE->REPEATED_DESIGNATED - MST 2, Port 1/1/1
MSTP: mstp_updtRcvdInfoWhileMsti mst=2, Port 1/1/1, rcvdInfoWhile 4->7
MSTP[0x175f35]: PRX RECEIVE->RECEIVE - Port 1/1/2
MSTP[0x175f35]: PIM CURRENT->RECEIVE - MST 0, Port 1/1/2
MSTP[0x175f35]: PIM RECEIVE->REPEATED_DESIGNATED - MST 0, Port 1/1/2
MSTP: mstp_updtRcvdInfoWhileCist mst=0, Port 1/1/2, rcvdInfoWhile 5->7
MSTP[0x175f35]: PIM CURRENT->RECEIVE - MST 2, Port 1/1/2
MSTP[0x175f35]: PIM RECEIVE->REPEATED_DESIGNATED - MST 2, Port 1/1/2
MSTP: mstp_updtRcvdInfoWhileMsti mst=2, Port 1/1/2, rcvdInfoWhile 4->7
deMSTP[0x175f3d]: PTX IDLE->TRANSMIT_PERIODIC - Port 1/1/1
MSTP[0x175f3d]: PTX IDLE->TRANSMIT_PERIODIC - Port 1/1/2
bug msMSTP[0x175f49]: PRX RECEIVE->RECEIVE - Port 1/1/1
MSTP[0x175f49]: PIM CURRENT->RECEIVE - MST 0, Port 1/1/1
MSTP[0x175f49]: PIM RECEIVE->REPEATED_DESIGNATED - MST 0, Port 1/1/1
MSTP: mstp_updtRcvdInfoWhileCist mst=0, Port 1/1/1, rcvdInfoWhile 5->7
MSTP[0x175f49]: PIM CURRENT->RECEIVE - MST 2, Port 1/1/1
MSTP[0x175f49]: PIM RECEIVE->REPEATED_DESIGNATED - MST 2, Port 1/1/1
MSTP: mstp_updtRcvdInfoWhileMsti mst=2, Port 1/1/1, rcvdInfoWhile 4->7
MSTP[0x175f49]: PRX RECEIVE->RECEIVE - Port 1/1/2
MSTP[0x175f49]: PIM CURRENT->RECEIVE - MST 0, Port 1/1/2
MSTP[0x175f49]: PIM RECEIVE->REPEATED_DESIGNATED - MST 0, Port 1/1/2
MSTP: mstp_updtRcvdInfoWhileCist mst=0, Port 1/1/2, rcvdInfoWhile 5->7
MSTP[0x175f49]: PIM CURRENT->RECEIVE - MST 2, Port 1/1/2
MSTP[0x175f49]: PIM RECEIVE->REPEATED_DESIGNATED - MST 2, Port 1/1/2
MSTP: mstp_updtRcvdInfoWhileMsti mst=2, Port 1/1/2, rcvdInfoWhile 4->7
tpMSTP[0x175f51]: PTX IDLE->TRANSMIT_PERIODIC - Port 1/1/1
MSTP[0x175f51]: PTX IDLE->TRANSMIT_PERIODIC - Port 1/1/2
eventMSTP[0x175f5d]: PRX RECEIVE->RECEIVE - Port 1/1/1
Parent topic: Debug Commands H - P