Packet Buffer Management

The following table lists the packet memory bandwidth and the total packet memory on ICX devices.

Packet Memory on ICX Devices

ICX Device Total Bandwidth Total Packet Memory
ICX 7550

348 Gbps (24/24P)

480 Gbps (48/48P/24ZP)

560 Gbps (24F/48F/48ZP)

8 MB
ICX 7650

480 Gbps

564 Gbps (IO 48ZP/48ZF)

328 Gbps (IO 48P)

8 MB
ICX 7850 2.0 Tbps

3.2 Tbps

32 MB
ICX 8100 300 Gbps 3 MB
ICX 8200 300 Gbps 3 MB

ICX 7850 devices support cut-through mode although they run in store-and-forward mode by default. If enabled, the cut-through-eligible packets are not buffered. If a packet must be buffered, it is buffered after Layer 2 and Layer 3 lookup. The packet priority is classified before buffering. On ICX 7850 devices, 1-Gbps ports always operate in store-and-forward mode, irrespective of the global switch mode configuration. On ICX 7850-48C devices, cut-through mode is supported only on Module 2 (ports 1/2/1 through 1/2/8 only).

ICX 7850-48C devices do not support cut-through switching on either 1-Gbps or 10-Gbps ports. Furthermore, when cut-through mode is enabled, while 1-Gbps and 10-Gbps ports remain in store-and-forward mode (the default), flow control is disabled on these ports in both directions.

Note: The ICX 7650, ICX 8100, and ICX 8200 devices support only store-and-forward mode for packet forwarding.

There are two independent packet admission mechanisms: ingress buffer management and egress buffer management.

Ingress Buffer Management

On the ICX 8100, and ICX 8200 devices, ingress buffer management tracks buffer utilization on a per-ingress-port basis.

  • Loss-less behavior through symmetric flow control is supported.
  • Buffers are reserved for high-priority traffic.

As these accounting structures reach their limits, incoming packets to the ingress port are dropped.

On the ICX 7650, ICX 8100, and ICX 8200 devices, there is a default profile for ingress buffer management, but it is not configurable because PFC is not supported.

The ingress buffer profile is not supported on the ICX 7550 and ICX 7850 devices.

Egress Buffer Management

This mechanism tracks buffer utilization on a per-egress port and priority basis. As these accounting structures reach their limits, packets that are destined to the congested egress port-priority are tail-dropped. The aim of the mechanism is to support fair access to the buffering resources among congested egress ports. Any incoming packet is counted only once per egress port regardless of whether it is unicast or multicast. Memory is logically divided into two sections:

  • Guaranteed (on a per-port-priority basis).
  • Shared on a per-port-priority basis for the ICX 7550, ICX 7650, ICX 7850, ICX 8100, and ICX 8200 devices.

On the ICX 7550, ICX 7650, ICX 7850, ICX 8100, and ICX 8200 devices, sharing is a ratio of the remaining buffers. You can configure the share level to determine the maximum number of buffers that an egress queue can use as a fraction of the total sharing pool. For example, if queue 4 is at level 4, it can use up to 1/9 of the total sharing buffers in the sharing pool. You can configure eight levels of sharing. The actual number of buffers that a queue can use depends on the number currently available in the system.